Lithographic apparatuses can be used, for example, in the manufacture of integrated circuits (ICs). In such a case, the mask may contain a circuit pattern corresponding to an individual layer of the IC, and this pattern can be imaged onto a target portion (e.g. comprising one or more dies) on a substrate (silicon wafer) that has been coated with a layer of radiation-sensitive material (resist). In general, a single wafer will contain a whole network of adjacent target portions that are successively irradiated via the projection system, one at a time. In one type of lithographic projection apparatus, each target portion is irradiated by exposing the entire mask pattern onto the target portion in one go; such an apparatus is commonly referred to as a wafer stepper. In an alternative apparatus, commonly referred to as a step-and-scan apparatus, each target portion is irradiated by progressively scanning the mask pattern under the projection beam in a given reference direction (the “scanning” direction) while synchronously scanning the substrate table parallel or anti-parallel to this direction. Since, in general, the projection system will have a magnification factor M (generally <1), the speed V at which the substrate table is scanned will be a factor M times that at which the mask table is scanned.
In a manufacturing process using a lithographic projection apparatus, a mask pattern is imaged onto a substrate that is at least partially covered by a layer of radiation-sensitive material (resist). Prior to this imaging step, the substrate may undergo various procedures, such as priming, resist coating and a soft bake. After exposure, the substrate may be subjected to other procedures, such as a post-exposure bake (PEB), development, a hard bake and measurement/inspection of the imaged features. This array of procedures is used as a basis to pattern an individual layer of a device, e.g., an IC. Such a patterned layer may then undergo various processes such as etching, ion-implantation (doping), metallization, oxidation, chemo-mechanical polishing, etc., all intended to finish off an individual layer. If several layers are required, then the whole procedure, or a variant thereof, will have to be repeated for each new layer. Eventually, an array of devices will be present on the substrate (wafer). These devices are then separated from one another by a technique such as dicing or sawing, whence the individual devices can be mounted on a carrier, connected to pins, etc.
For the sake of simplicity, the projection system may hereinafter be referred to as the “lens”; however, this term should be broadly interpreted as encompassing various types of projection systems, including refractive optics, reflective optics, and catadioptric systems, for example. The radiation system may also include components operating according to any of these design types for directing, shaping or controlling the projection beam of radiation, and such components may also be referred to below, collectively or singularly, as a “lens”. Further, the lithographic apparatus may be of a type having two or more substrate tables (and/or two or more mask tables). In such “multiple stage” devices the additional tables may be used in parallel, or preparatory steps may be carried out on one or more tables while one or more other tables are being used for exposures.
The photolithographic masks referred to above comprise geometric patterns corresponding to the circuit components to be integrated onto a silicon wafer. The patterns used to create such masks are generated utilizing CAD (computer-aided design) programs, this process often being referred to as EDA (electronic design automation). Most CAD programs follow a set of predetermined design rules in order to create functional masks. These rules are set by processing and design limitations. For example, design rules define the space tolerance between circuit devices (such as gates, capacitors, etc.) or interconnect lines, so as to ensure that the circuit devices or lines do not interact with one another in an undesirable way. The design rule limitations are typically referred to as “critical dimensions” (CD). A critical dimension of a circuit can be defined as the smallest width of a line or hole or the smallest space between two lines or two holes. Thus, the CD determines the overall size and density of the designed circuit. Of course, one of the goals in integrated circuit fabrication is to faithfully reproduce the original circuit design on the wafer (via the mask).
As noted, microlithography is a central step in the manufacturing of semiconductor integrated circuits, where patterns formed on semiconductor wafer substrates define the functional elements of semiconductor devices, such as microprocessors, memory chips etc. Similar lithographic techniques are also used in the formation of flat panel displays, micro-electro mechanical systems (MEMS) and other devices.
As semiconductor manufacturing processes continue to advance, the dimensions of circuit elements have continually been reduced while the amount of functional elements, such as transistors, per device has been steadily increasing over decades, following a trend commonly referred to as ‘Moore's law’. At the current state of technology, critical layers of leading-edge devices are manufactured using optical lithographic projection systems known as scanners that project a mask image onto a substrate using illumination from a deep-ultraviolet laser light source, creating individual circuit features having dimensions well below 100 nm, i.e. less than half the wavelength of the projection light.
This process in which features with dimensions smaller than the classical resolution limit of an optical projection system are printed, is commonly known as low-k1 lithography, according to the resolution formula CD=k1×λ/NA, where λ is the wavelength of radiation employed (currently in most cases 248 nm or 193 nm), NA is the numerical aperture of the projection optics, CD is the ‘critical dimension’—generally the smallest feature size printed—and k1 is an empirical resolution factor. In general, the smaller k1, the more difficult it becomes to reproduce a pattern on the wafer that resembles the shape and dimensions planned by a circuit designer in order to achieve particular electrical functionality and performance. To overcome these difficulties, sophisticated fine-tuning steps are applied to the projection system as well as to the mask design. These include, for example, but not limited to, optimization of NA and optical coherence settings, customized illumination schemes, use of phase shifting masks, optical proximity correction in the mask layout, or other methods generally defined as ‘resolution enhancement techniques’ (RET).
As one important example, optical proximity correction (OPC, sometimes also referred to as ‘optical and process correction’) addresses the fact that the final size and placement of a printed feature on the wafer will not simply be a function of the size and placement of the corresponding feature on the mask. It is noted that the terms ‘mask’ and ‘reticle’ are utilized interchangeably herein. For the small feature sizes and high feature densities present on typical circuit designs, the position of a particular edge of a given feature will be influenced to a certain extent by the presence or absence of other adjacent features. These proximity effects arise from minute amounts of light coupled from one feature to another. Similarly, proximity effects may arise from diffusion and other chemical effects during post-exposure bake (PEB), resist development, and etching that generally follow lithographic exposure.
In order to ensure that the features are generated on a semiconductor substrate in accordance with the requirements of the given target circuit design, proximity effects need to be predicted utilizing sophisticated numerical models, and corrections or pre-distortions need to be applied to the design of the mask before successful manufacturing of high-end devices becomes possible. In a typical high-end design almost every feature edge requires some modification in order to achieve printed patterns that come sufficiently close to the target design. These modifications may include shifting or biasing of edge positions or line widths as well as application of ‘assist’ features that are not intended to print themselves, but will affect the properties of an associated primary feature.
Double patterning (DP) lithography is one of the methods to effectively overcome the resolution limit of lithographic exposure apparatus, especially, when further increase of NA is no longer a feasible option to enhance printing quality of the critical/non-critical features in a ‘feature-dense’ layout. In general, in double patterning lithography, dense patterns, whose individual feature CD and/or inter-feature pitch is below the resolution limit of the lithography apparatus, are split in two parts (this process is referred to as “coloring”), such that, independently in each part, there is no resolution-related problems to overcome during pattern printing. The parts are patterned sequentially, interspersing features printed in the first lithography with features printed in the second lithography, to reproduce the entire pattern.
The existing splitting framework, specially for full-chip double patterning, may use a rule-based splitting algorithm followed by stitching and/or OPC(Optical Proximity Correction). The rule-based splitting algorithm splits the design layout into two sub-layouts based on a set of rules according to imaging system limitations. Then the stitching and/or OPC algorithm is applied independently for each sub-layout.
Source mask optimization (SMO) is a process to optimize source and mask (i.e. design layout) simultaneously to achieve the better resolution and/or processing window (PW) for a given design layout. Reduction of total runtime of SMO can be achieved if the design layout of the mask is optimized with respect to the source. In general, to lower the computation cost and time, a critical set of design patterns is either provided by users or automatically selected by an intelligent algorithm. SMO is performed only on the selected critical design set of design patterns to get the optimized source. Then, optionally, the full chip mask optimization (FMO) is used to optimize the full chip design layout given the optimized source. A lithography manufacturability check (LMC) may also be optionally done to add the hotspots into selected critical design pattern set.
Thus far, SMO and DP have not been integrated to achieve even better imaging performance in a more computationally efficient way. Therefore, there exists a need for integrating SMO and DP in a unified process flow. Furthermore, there exists a need to co-optimize the design layout for other optical characteristics, such as the projection optics in a lithography apparatus.